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information in this document is provided solely to enable use of intel products. intel assumes no li ability whatsoever, including infringe- ment of any patent or copyright, for sale and use of intel products except as provided in intels terms and conditions of sale for such products. information contained herein supersedes previously published specifications on these devices from intel. ? intel corporation, 1994 september 1994 order number: 272419-003 intel386? sxsa embedded microprocessor n static intel386? cpu core low power consumption operating power supply 4.5v to 5.5v - 25 and 33 mhz 4.75v to 5.25v - 40 mhz operating frequency sa-40 = 40 mhz sa-33 = 33 mhz sa-25 = 25 mhz n clock freeze mode allows clock stopping at any time n full 32-bit internal architecture 8-, 16-, 32-bit data types 8 general purpose 32-bit registers n runs intel386 architecture software in a cost-effective, 16-bit hardware environment runs same applications and operating systems as the intel386 sx and intel386 dx processors object code compatible with 8086, 80186, 80286, and intel386 processors n ttl-compatible inputs n high-performance 16-bit data bus two-clock bus cycles address pipelining allows use of slower, inexpensive memories n integrated memory management unit (mmu) virtual memory support optional on-chip paging 4 levels of hardware-enforced protection mmu fully compatible with those of the 80286 and intel386 dx processors n virtual 8086 mode allows execution of 8086 software in a protected and paged system n large, uniform address space 16 megabyte physical 64 terabyte virtual 4 gigabyte maximum segment size n numerics support with intel387? sx and intel387 sl math coprocessors n on-chip debugging support including breakpoint registers n complete system development support n high-speed chmos technology n 100-pin plastic quad flatpack package the intel386? sxsa embedded microprocessor is a 5-volt, 32-bit, fully static cpu with a 16-bit external data bus and a 24-bit external address bus. the intel386 sxsa cpu brings the vast software library of the intel386 architecture to embedded systems. it provides the performance benefits of 32-bit programming with the cost savings associated with 16-bit hardware systems. the intel386 sxsa microprocessor is manufactured on intels 0.8-micron chmos v process. this process provides high performance and low power consumption for power-sensitive applications. figure 3 and figure 4 illustrate the flexibility of low power devices with respect to temperature and frequency relationships.
intel386? sxsa embedded microprocessor 2 figure 1. intel386? sxsa microprocessor block diagram decode and sequencing control rom status flags alu alu control control prefetcher/ limit checker 16-byte code queue code stream 32 segmentation unit paging unit bus control 32 32 32 32 27 instruction prefetch control physical address bus adder page cache control and attribute pla instruction decoder 3-decoded instruction queue instruction predecode mux/ trans- ceivers pipeline/ bus size control address driver request prioritizer 3-input adder descriptor register limit and attribute pla linear address bus displacement bus barrel shifter/ adder multiply/ divide register file protection test unit a2298-01 internal control bus 32 code fetch/page table fetch effective address bus effective address bus dedicated alu bus hold, reset intr, nmi error# busy#,hlda ble#, bhe# a23:1 m/io#, d/c# w/r#, lock# ads#, na# ready# d15:0
intel386? sxsa embedded microprocessor 3 1.0 pin assignment figure 2. intel386? sxsa microprocessor pin assignment (pqfp) note: nc = no connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a20 a19 a18 a17 vcc a16 vcc vss vss a15 a14 a13 vss a12 a11 a10 a9 a8 vcc a7 a6 a5 a4 a3 a2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 d0 vss hlda hold vss na# ready# vcc vcc vcc vss vss vss vss clk2 ads# ble# a1 bhe# nc vcc vss m/io# d/c# w/r# d1 d2 vss vcc d3 d4 d5 d6 d7 vcc d8 d9 d10 d11 d12 vss vcc d13 d14 d15 a23 a22 vss vss a21 lock# nc flt# nc nc nc vcc reset busy# vss error# pereq nmi vcc intr vss vcc nc nc nc nc nc vcc vss vss top view a2297-0a
intel386? sxsa embedded microprocessor 4 table 1. pin assignment pin symbol pin symbol pin symbol pin symbol 1 d0 26 lock# 51 a2 76 a21 2 v ss 27 nc 52 a3 77 v ss 3 hlda 28 flt# 53 a4 78 v ss 4 hold 29 nc 54 a5 79 a22 5 v ss 30 nc 55 a6 80 a23 6 na# 31 nc 56 a7 81 d15 7 ready# 32 v cc 57 v cc 82 d14 8 v cc 33 reset 58 a8 83 d13 9 v cc 34 busy# 59 a9 84 v cc 10 v cc 35 v ss 60 a10 85 v ss 11 v ss 36 error# 61 a11 86 d12 12 v ss 37 pereq 62 a12 87 d11 13 v ss 38 nmi 63 v ss 88 d10 14 v ss 39 v cc 64 a13 89 d9 15 clk2 40 intr 65 a14 90 d8 16 ads# 41 v ss 66 a15 91 v cc 17 ble# 42 v cc 67 v ss 92 d7 18 a1 43 nc 68 v ss 93 d6 19 bhe# 44 nc 69 v cc 94 d5 20 nc 45 nc 70 a16 95 d4 21 v cc 46 nc 71 v cc 96 d3 22 v ss 47 nc 72 a17 97 v cc 23 m/io# 48 v cc 73 a18 98 v ss 24 d/c# 49 v ss 74 a19 99 d2 25 w/r# 50 v ss 75 a20 100 d1
intel386? sxsa embedded microprocessor 5 2.0 pin descriptions table 2 lists the intel386 sxsa microprocessor pin descriptions. the following definitions are used in the pin descriptions: # the named signal is active low. i input signal. o output signal. i/o input and output signal. p power pin. g ground pin. table 2. pin descriptions symbol type pin name and function a23:1 o 80C79, 76C72, 70, 66C64 62C58, 56C51, 18 address bus outputs physical memory or port i/o addresses. ads# o 16 address status indicates that the processor is driving a valid bus-cycle definition and address onto its pins (w/r#, d/c#, m/io#, bhe#, ble#, and a23:1). bhe# o 19 byte high enable indicates that the processor is transferring a high data byte. ble# o 17 byte low enable indicates that the processor is transferring a low data byte. busy# i 34 busy indicates that the math coprocessor is busy. clk2 i 15 clk2 provides the fundamental timing for the device. d/c# o 24 data/control indicates whether the current bus cycle is a data cycle (memory or i/o) or a control cycle (interrupt acknowledge, halt, or code fetch). when d/c# is high, the bus cycle is a data cycle; when d/c# is low, the bus cycle is a con- trol cycle. d15:0 i/o 81C83, 86C90, 92C96, 99C100, 1 data bus inputs data during memory read, i/o read, and interrupt acknowledge cycles and outputs data during mem- ory and i/o write cycles. error# i 36 error indicates that the math coprocessor has an error condi- tion. flt# i 28 float forces all bidirectional and output signals, including hlda, to a high-impedance state. hlda o 3 bus hold acknowledge indicates that the cpu has surren- dered control of its local bus to another bus master. hold i 4 bus hold request allows another bus master to request con- trol of the local bus. intr i 40 interrupt request is a maskable input that causes the cpu to suspend execution of the current program and then exe- cute an interrupt acknowledge cycle.
intel386? sxsa embedded microprocessor 6 lock# o 26 bus lock prevents other system bus masters from gaining control of the system bus while it is active (low). m/io# o 23 memory/io indicates whether the current bus cycle is a mem- ory cycle or an input/output cycle. when m/io# is high, the bus cycle is a memory cycle; when m/io# is low, the bus cycle is an i/o cycle. na# i 6 next address requests address pipelining. nc 20, 27, 29C31, 43C47 no connection should always be left unconnected. connect- ing a nc pin may cause the processor to malfunction or cause your application to be incompatible with future steppings of the device. nmi i 38 nonmaskable interrupt request is a nonmaskable input that causes the cpu to suspend execution of the current pro- gram and execute an interrupt acknowledge function. pereq i 37 processor extension request indicates that the math coprocessor has data to transfer to the processor. ready# i 7 bus ready indicates that the current bus cycle is finished and the external device is ready to accept more data from the pro- cessor. reset i 33 reset suspends any operation in progress and places the processor into a known reset state. w/r# o 25 write/read indicates whether the current bus cycle is a write cycle or a read cycle. when w/r# is high, the bus cycle is a write cycle; when w/r# is low, it is a read cycle. v cc p 8C10, 21, 32, 39, 42, 48, 57, 69, 71, 84, 91, 97 system power provides the nominal dc supply input. v ss g 2, 5, 11C14, 22 35, 41, 49C50, 63, 67C68, 77C78, 85, 98 system ground provides the 0v connection from which all inputs and outputs are measured. table 2. pin descriptions (continued) symbol type pin name and function
intel386? sxsa embedded microprocessor 7 3.0 design considerations this section describes the static intel386 sxsa microprocessor instruction set, component and revision identifier, and package thermal specifica- tions. 3.1. instruction set the static intel386 sxsa microprocessor uses the same instruction set as the dynamic intel386 sx microprocessor. however, the static intel386 sxsa microprocessor requires more clock cycles than the dynamic intel386 sx microprocessor to execute some instructions. table 4 lists these instructions and the static intel386 sxsa microprocessor execution times. for the equivalent dynamic intel386 sx microprocessor execution times, refer to the instruction set clock count summary table in the intel386? sx microprocessor data sheet (order number 240187). 3.2. component and revision identifier to assist users, the microprocessor holds a component identifier and revision identifier in its dx register after reset. the upper 8 bits of dx hold the component identifier, 23h. (the lower nibble, 3h, identifies the intel386 architecture, while the upper nibble, 2h, identifies the second member of the intel386 microprocessor family.) the lower 8 bits of dx hold the revision level identifier. the revision identifier will, in general, chronologically track those component steppings that are intended to have certain improvements or distinction from previous steppings. the revision identifier will track that of the intel386 cpu whenever possible. however, the revision identifier value is not guaranteed to change with every stepping revision or to follow a completely uniform numerical sequence, depending on the type or intent of the revision or the manufacturing materials required to be changed. intel has sole discretion over these characteristics of the component. the initial revision identifier for the static intel386 sxsa microprocessor is 09h. 3.3. package thermal specifications static intel386 sxsa microprocessor is specified for operation with case temperature (t case ) as specified in the dc specifications on page 9. the case temperature can be measured in any environment to determine whether the micropro- cessor is within the specified operating range. the case temperature should be measured at the center of the top surface opposite the pins. an increase in the ambient temperature (t a ) causes a proportional increase in the case temperature (t case ) and the junction temperature (t j ). see figures 3 and figures 4 for case and ambient temperature relationships to frequency. a packaged device produces thermal resistance between junction and case temperatures ( q jc ) and between junction and ambient temperatures ( q ja ). the relationships between the temperature and thermal resistance parameters are expressed by these equations (p = power dissipated as heat = v cc i cc ): 1. t j = t case + p q jc 2. t a = t j C p q ja 3. t case = t a + p [ q ja C q jc ] a safe operating temperature can be calculated from equation 1 by using the maximum safe t j of 115 c, the maximum power drawn by the chip in the specific design, and the q jc value from table 3. the q j a value depends on the airflow (measured at the top of the chip) provided by the system venti- lation. the q j a values are given for reference only and are not guaranteed. table 3. thermal resistances (0c/w) q ja , q jc pkg q jc q ja versus airflow (ft/min) 0 100 200 100 pqfp 5.1 46.0 44.8 41.2
intel386? sxsa embedded microprocessor 8 table 4. intel386? sxsa microprocessor instruction execution times (in clock counts) instruction clock count virtual 8086 mode (note 1) real address mode or virtual 8086 mode protected virtual address mode (note 3) popa 28 35 in: fixed port variable port 27 28 14 15 7/29 8/29 out: fixed port variable port 27 28 14 15 7/29 9/29 ins 30 17 9/32 outs 31 18 10/33 rep ins 31+6n (note 2) 17+6n (note 2) 10+6n/32+6n (note 2) rep outs 30+8n (note 2) 16+8n (note 2) 10+8n/31+8n (note 2) hlt 7 7 mov c0, reg 10 10 notes: 1. the clock count values in this column apply if i/o permission allows i/o to the port in virtual 8086 mode. if the i/o bit map denies permission, exception fault 13 occurs; see clock counts for the int 3 instruction in the instruction set clock count summary table in the intel386? sx microprocessor data sheet (order number 240187). 2. n = the number of times repeated. 3. when two clock counts are listed, the smaller value refers to a register operand and the larger value refers to a memory operand.
intel386? sxsa embedded microprocessor 9 4.0 dc specifications absolute maximum ratings* storage temperature ................................ C65c to +150c case temperature under bias ................. C65c to +112c supply voltage with respect to v ss ............... C0.5v to 6.5v voltage on other pins .......................... C0.5v to v cc + 0.5v operating conditions* v cc (digital supply voltage - 25 and 33 mhz) ...4.5v to 5.5v v cc (digital supply voltage - 40 mhz) ...........4.75v to 5.25v t case minimum (case temperature under bias) ......... 0c t case maximum ......................................... see figure 4 operating frequency ................................ 0 mhz to 40 mhz notice : this document contains information on products in the sampling and initial production phases of development. the specifications are sub- ject to change without notice. verify with your local intel sales office that you have the latest data sheet before finalizing a design. * warning : stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. table 5. dc characteristics symbol parameter min. max. unit test condition v il input low voltage C0.3 +0.8 v v ih input high voltage 2.0 v cc + 0.3 v v ilc clk2 input low voltage C0.3 +0.8 v v ihc clk2 input high voltage v cc C 0.8 v cc + 0.3 v v ol output low voltage 0.45 v i ol = 5 ma v oh output high voltage 2.4 v cc C 0.5 v v i oh = C1 ma i oh = C0.2 ma i li input leakage current (for all pins except pereq, busy#, flt#, error#) 15 a 0 v in v cc i ih input leakage current (pereq) 150 a v ih = 2.4v (note 1) i il input leakage current (busy#, flt#, error#) C120 a v il = 0.45v (note2) i lo output leakage current 15 a 0.45v v out v cc i cc supply current clk2 = 80 mhz, clk = 40 mhz clk2 = 66 mhz, clk = 33 mhz clk2 = 50 mhz, clk = 25 mhz 275 225 175 ma ma ma (notes 3, 4) typical = 200 ma typical = 175 ma typical = 140 ma i ccf standby current (freeze mode) 150 a typical = 10 a (notes 3 4) c in input capacitance 10 pf f c = 1 mhz (note 5) c out output or i/o capacitance 12 pf f c = 1 mhz (note 5) c clk clk2 capacitance 20 pf f c = 1 mhz (note 5) notes: 1. pereq input has an internal weak pull-down resistor. 2. busy#, flt# and error# inputs each have an internal weak pull-up resistor. 3. i cc max measurement at worst-case frequency, v cc , and temperature with reset active. 4. i cc typical and i ccf typical are measured at nominal v cc and are not fully tested. 5. not fully tested.
intel386? sxsa embedded microprocessor 10 figure 3. ambient temperature vs. frequency at zero air flow and t j = 115 c a2586-01 100 75 50 25 t (?c) a operating frequency (mhz) 12 16 20 25 33 40 90 85 80 70 58 45
intel386? sxsa embedded microprocessor 11 figure 4. case temperature vs. frequency at t j = 115 c a2587-01 115 105 t (?c) c operating frequency (mhz) 12 16 20 25 33 40 110 112 111.5 111 110 108.5 107
intel386? sxsa embedded microprocessor 12 5.0 ac specifications table 6 lists output delays, input setup require- ments, and input hold requirements. all ac specifi- cations are relative to the clk2 rising edge crossing the 2.0v level. figure 5 shows the measurement points for ac specifications. inputs must be driven to the indicated voltage levels when ac specifications are measured. output delays are specified with minimum and maximum limits measured as shown. the minimum delay times are hold times provided to external circuitry. input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. within the sampling window, a synchronous input signal must be stable for correct operation. outputs ads#, w/r#, d/c#, mi/o#, lock#, bhe#, ble#, a23:a1 and hlda change only at the beginning of phase one. d15:0 (write cycles) change only at the beginning of phase two. the ready#, hold, busy#, error#, pereq, flt# and d15:0 (read cycles) inputs are sampled at the beginning of phase one. the na#, intr and nmi inputs are sampled at the beginning of phase two.
intel386? sxsa embedded microprocessor 13 figure 5. drive levels and measurement points for ac specifications a b tx valid output n+1 a a a a b min max c d clk2 outputs (a23:1,bhe# ble#,ads#,mi/o# d/c#w/r#,lock# hlda) outputs (d15:0) inputs (n/a#,intr nmi) inputs (ready#,hold flt#,error# busy#,pereq d15:0) legend a - 1.5v b - 2.0v a - maximum output delay spec b - minimum output delay spec c - minimum input setup spec d - minimum input hold spec ph1 ph2 3.0v 0v valid output n a b valid output n+1 a a min max valid output n valid input a a c d 3.0v 0v valid input a2296-02
intel386? sxsa embedded microprocessor 14 table 6. ac characteristics symbol parameter 40 mhz 33 mhz 25 mhz test condition min. (ns) max. (ns) min. (ns) max . (ns) min. (ns) max. (ns) operating frequency 0 40 0 33 0 25 mhz (note 1) t1 clk2 period 12.5 15 20 t2a clk2 high time 4.5 6.25 7 (note 2) t2b clk2 high time 3.5 4 4 (note 2) t3a clk2 low time 4.5 6.25 7 (note 2) t3b clk2 low time 3.5 4.5 5 (note 2) t4 clk2 fall time 4 4 7 (note 2) t5 clk2 rise time 4 4 7 (note 2) t6 a23:1 valid delay 4 13 4 15 4 17 c l = 50 pf t7 a23:1 float delay 4 20 4 20 4 30 (note 3) t8 bhe#, ble#, lock# valid delay 4 134 154 17c l = 50 pf t9 bhe#, ble#, lock# float delay 4 20 4 20 4 30 (note 3) t10 w/r#, m/io#, d/c#, ads# valid delay 4 134 154 17c l = 50 pf t11 w/r#, m/io#, d/c#, ads# float delay 4 20 4 20 4 30 (note 3) t12 d15:0 write data valid delay 7 187 237 23c l = 50 pf (note 5) t12a d15:0 write data hold time 222c l = 50 pf t13 d15:0 write data float delay 4 17 4 17 4 22 (note 3) t14 hlda valid delay 4 17 4 20 4 22 c l = 50 pf t15 na# setup time 5 5 5 t16 na# hold time 2 2 3 t19 ready#setup time 7 7 9 t20 ready#hold time 4 4 4 t21 d15:0 read setup time 457 notes: 1. tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. these are not tested. they are guaranteed by characterization. 3. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not fully tested. 4. these inputs may be asynchronous to clk2. the setup and hold specifications are given for testing purposes to ensure recognition within a specific clk2 period. 5. minimum time not 100% tested.
intel386? sxsa embedded microprocessor 15 t22 d15:0 read hold time 335 t23 hold setup time 4 9 9 t24 hold hold time 2 2 3 t25 reset setup time 4 5 8 t26 reset hold time 2 2 3 t27 nmi, intr setup time 5 5 6 (note 4) t28 nmi, intr hold time 5 5 6 (note 4) t29 pereq, error#, busy#, flt# setup time 5 5 6 (note 4) t30 pereq, error#, busy#, flt# hold time 4 4 5 (note 4) table 6. ac characteristics (continued) symbol parameter 40 mhz 33 mhz 25 mhz test condition min. (ns) max. (ns) min. (ns) max . (ns) min. (ns) max. (ns) notes: 1. tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. these are not tested. they are guaranteed by characterization. 3. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not fully tested. 4. these inputs may be asynchronous to clk2. the setup and hold specifications are given for testing purposes to ensure recognition within a specific clk2 period. 5. minimum time not 100% tested.
intel386? sxsa embedded microprocessor 16 figure 6. ac test loads figure 7. clk2 waveform a2200-0a cpu output c l clk2 t 4 a b c a = vcc -.8 b = 2.0v c = .8v t 3b t 3a t 1 t 2a t 2b t 5 a2291-0a
intel386? sxsa embedded microprocessor 17 figure 8. ac timing waveforms input setup and hold timing clk2 tx tx tx ready# hold d15:0 (input) busy# error# pereq flt# na# intr nmi ph2 ph1 ph2 ph1 t 19 t 20 t 23 t 24 t 21 t 22 t 29 t 30 t 15 t 16 t 27 t 28 a2292-01
intel386? sxsa embedded microprocessor 18 figure 9. ac timing waveforms output valid delay timing clk2 tx tx tx bhe#, ble# lock# w/r#, m/io# d/c#, ads# a23:1 d15:0 (output) ph2 ph1 ph2 ph1 min valid n+1 valid n max min valid n+1 valid n max min valid n+1 valid n max min valid n+1 max valid n hlda t 8 t 10 t 6 t 12, t 12a a2293-01
intel386? sxsa embedded microprocessor 19 figure 10. ac timing waveforms output float delay and hlda valid delay timing clk2 ti or t1 bhe#, ble# lock# w/r#, m/io# d/c#, ads# a23:1 d15:0 ph2 ph1 ph2 ph1 min max hlda ph2 th min max (high z) min max min max (high z) min max min max (high z) min max min max (high z) t 13 also applies to data float when write cycle is followed by read or idle. min max min max t 8 t 10 t 6 t 11 t 7 t 9 t 13 t 14 t 14 t 12 a2294-01
intel386? sxsa embedded microprocessor 20 figure 11. ac timing waveforms reset setup and hold timing and internal phase 6.0 revision history this -003 data sheet contains the following changes from the -002 version. ? changed v cc at 40 mhz to 4.75v to 5.25v (pages 1 and 9) ? renamed powerdown mode to clock freeze mode on page one. ? added clarifications to figure 1. ? corrected pin numbering for a23:1 in table 2 ? changed the first sentence in section 3.3 from ...on page 12 to ...on page 9. ? changed the first sentence on page 12 from table 7 lists... to table 6... also changed the first sentence of the fourth paragraph on page 12 from ...a25:1 to ...a23:1. clk2 reset ph2 ph1 ph2 or ph1 ph2 or ph1 reset initialization sequence t 26 t 25 a2205-0a

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